Report: AMD Carrizo APUs To Get Stacked On-Die Memory

Is AMD’s HSA arriving with force in the forthcoming Carrizo APUs?

Possibly it really is an strange resource, but Bits ‘n Chips from Italy has reported that AMD might be employing stacked-DRAM memory in its impending Carrizo APUs. In alone, this should not be specifically stunning – AMD is quite actively pushing the Heterogeneous Method Architecture.

The concept of the Heterogeneous Method Architecture is that the CPU and GPU cores all have equal access to the technique memory, exactly where they can function together without each and every main currently being assigned a distinct component of the memory, but the place both are in a position to tackle any part of the memory at any time. This claims to let for considerably larger performance ranges, where the GPU can take treatment of hugely parallelized jobs, and the CPU can consider treatment of serial tasks. These kinds of an architecture will truly glow when some of the memory is on-die, providing considerably decrease latencies.

The Italian resource signifies that obtaining stacked on-die memory will direct to far more value-successful performance compared with on-die L3 cache. This will certainly be owing to the a lot more successful use of the provided hardware. The bulk of system memory would still be positioned on DDR3, mainly due to the fact on-die memory will only include up to somewhere about 128 MB or 256 MB. The report also mentions the potential to stick to DDR3 for the method memory, as opposed to the much far more costly DDR4.

According to the report, the Carrizo APUs will be fabricated on a 28 nm lithographic process, whilst the stacked-DRAM will be fabricated on a twenty nm approach.

Other resources also reveal that some of the Carrizo APUs will have the FCH on-die. We wonder how prolonged it will get ahead of we have all the essential elements on-die, basically creating SoC’s (Program-on-a-Chip).

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